Siemens EDA

May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
May 19, 2021

Understand how DO-254 defines verification for avionics

The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
May 13, 2021

Siemens extends Solido’s reach into IP validation with Fractal

Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
April 19, 2021

Hardware verification puts software first

Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
Article  |  Topics: Blog Topics  |  Tags: , , , ,   |  Organizations:
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
April 8, 2021

Navigating the Siemens EDA portfolio

The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations:
April 6, 2021

Siemens cloud tool streamlines DFM for PCBs

Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
Article  |  Topics: Blog - PCB  |  Tags: , , , ,   |  Organizations:
March 26, 2021

Siemens brings emulation and prototyping together in hardware-assisted verification

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
March 18, 2021

DVCon to stick with virtual for Europe as US event highlights paper award

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,

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