Coherency verification for CXL
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
Siemens EDA
TSMC certifies Aprisa for N5 and N4
TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.
Siemens brings ReadyStart RTOS to RISC-V
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Navigate variables and lifetimes in SystemVerilog
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Go inside proposals for common chiplet models
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
Verifying the new namespace storage options in NVMe 2.0
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Learn strategies for better measurement and test in simulation-based PCB design
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Capturing connectivity for assembly verification in 2.5D and 3D design
Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
How digital twin evaluations optimize STCO-based design
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Silicon Photonics verification case study from UC-Davis and Texas A&M
Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.