Cadence Design Systems

April 7, 2014
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DAC 2014 offers free exhibit entry for three days

The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags:   |  Organizations: , ,
March 21, 2014

Mentor buys BDA for AMS portfolio

Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations: ,
March 5, 2014

Visual timing tool focuses on high-speed PCB signals

Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
February 24, 2014

Cadence uses SQL to boost verification manager capacity

Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
January 14, 2014

Cadence updates Incisive with formal, CRV, wreal additions

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
November 12, 2013

Cadence ties IR drop into static timing analysis

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 23, 2013

3D-IC focus for GSA’s Taipei Memory+ event next week

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
October 16, 2013

CDNLive calls out for papers

Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.
Article  |  Topics: Conferences, Blog - EDA, Embedded, PCB  |  Tags: ,   |  Organizations:
October 11, 2013

Verification Futures rolls out in Europe next month

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.

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