April 7, 2014
The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
March 21, 2014
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
March 5, 2014
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
February 24, 2014
Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
February 6, 2014
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
January 14, 2014
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
November 12, 2013
Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
October 23, 2013
Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
October 16, 2013
Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.
October 11, 2013
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.