Cadence ties IR drop into static timing analysis

By Chris Edwards |  1 Comment  |  Posted: November 12, 2013
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

Cadence Design Systems claims to have closed the loop between static timing and IC-level power-integrity analysis with the launch of its Voltus tool. The software deploys parallelism to speed up full-chip analysis so that the true effects of voltage droop can be seen on different process corners during the sign-off process.

As large-scale SoCs now routinely switch in and out of power states, there is huge potential for IR drop issues to emerge, particularly if lots of cells coming out of retention mode interferes with a nearby core trying to deal with a surge of activity, pushing it to consume higher levels of current.

“Technology hasn’t kept up with requirements. We now have more process corners to deal with and more operating modes to consider,” said KT Moore, group director at Cadence. “Voltus is the first power-integrity tool to integrate with static timing analysis. What the customer really wants to know is the impact of IR drop on the setup and hold timings on critical paths.”

To deal with the volume of data that full-chip power analysis can generate, Cadence developed a number of parallel algorithms – similar to the approach that the company took with Tempus earlier in the year. The company claims Spice-like accuracy but with runtimes up to ten times shorter than with existing tools.

“The philosophy behind the tool is that we wanted to take a holistic view of the problem and take advantage of the architecture that compute servers are coming out with,” said Moore.

Power meets timing

As the names Tempus and Voltus may suggest, “these things have been architected to work together”, said Moore. “A customer using Tempus and Voltus together can get a better sense of confidence in design closure. Although we looked at how to work well within the Cadence infrastructure, we also looked at how to work well with the rest of the ecosystem.”

Moore said Voltus is designed to take into account the kind of power problems that can afflict 3D-stacked designs, such as themal hotspots. The tool is intended to tie in with the Sigrity tools developed for package-level analysis that Cadence bought last year.

“With decoupling capacitors and power switches, you really can’t take them for granted anymore. The problem is how to deal with all the data in what is a highly coupled problem,” said Moore.

Although designed to provide sign-off accuracy, Cadence’s aim is to bring power analysis earlier in the design flow, to the floorplanning stage at least.

“Power is a really bad problem to find out about late in the design cycle. You tell your manager you are close to tape-out and then somebody runs IR drop analysis and suddenly finds there is a problem,” said Moore.

A further integration is with the Palladium emulator-based verification environment – vectors produced by system-level testbenches can be fed to Voltus to see how they affect the power grid.

The parallelism is intended to provide Voltus with high capacity. In principle it can run large designs flat, although hierarchical techniques are likely to support the biggest chips better. “We haven’t had to run up to one billion instances yet, but we have done designs of hundreds of millions of instances. One customer who has taped out using Voltus ran with several hundred million instances,” Moore said

Although Voltus was developed for sub-30nm processes, Moore said: “I believe that this will roll back to older process nodes. I would expect that once customers get their hands on this, it won’t just be limited to advanced nodes.”

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