Cadence Design Systems has developed a timing-analysis environment for its Allegro PCB Designer software that is intended to deal with low-voltage, high-speed protocols such as DDR3/DDR4, PCI Express, and SATA.
The TimingVision environment uses an embedded timing engine to analyze the interface structure and develop timing goals to help designers visualize real-time delay and phase information. The idea behind TimingVision is to reduce the amount of manual editing needed as well as overall implementation time, and designer effort. The tool is designed to work with the Cadence Sigrity power-aware signal-integrity analysis tool to speed up the tuning of board designs to comply with standard interfaces and cut the amount of time spent on trial-and-error fixes.
TimingVision provides dynamic feedback on the active and related signals during edits on the design canvas and performs phase tuning to compensate both static and dynamic phase constraints on a selected set of differential pairs as well as delay tuning to compensate for relative propagation delay between a series of associated traces, such as those in a byte lane between processor and memory, while keeping within total etch-length constraints as specified for the design.
Cadence has produced a video describing the features on its YouTube channel, which we have also embedded above, that shows how a designer can highlight trace bundles and have predefined types of jogs and bumps added to some of them to balance phase and delay.
“Using this new Allegro technology ended our frustrations over all of the time we were spending on routing and tuning. All of the hours we’re saving as a team can be directed toward new project requests for the business,” said Sky Huang, deputy director of computer-aided engineering at Pegatron.
TimingVision, along with the auto-interactive routing environment, is available now as part of the Allegro PCB High-Speed Option.