Cadence Design Systems

October 10, 2013

Cadence launches IP cores for 60GHz wireless and consumer audio

Cadence Design Systems has launched IP cores for high-end mobile audio as well as gigasample ADCs for 28nm to support 60GHz wireless.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
October 9, 2013

Cadence parallelizes FastSpice for large-scale mixed-signal checks

Cadence Design Systems has developed a version of its Spectre FastSpice tool that splits simulation across many computers without manually cutting the design into segments.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
October 8, 2013

Wreal and Open Access star in mixed-signal summit

Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
October 2, 2013

Old problems on a new scale

For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
September 10, 2013

Speed boost for Palladium emulators

Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
September 3, 2013

ARM buys securable display controller

ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
August 12, 2013

CDNLive Boston to tackle mixed-signal design, host exhibit

Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
July 30, 2013

Three Accellera proposals aim for better TLM

Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
July 15, 2013

Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
June 4, 2013

Timing signoff: maybe it’s time to get rid of the clock

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors