‘Known unknowns’ and the Cadence take on verification IP
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
Cadence Design Systems
Using verification IP to master AMBA and wider protocol proliferation
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Synopsys buys EVE and the death of dogma
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
Cadence updates Allegro and Orcad
Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.
DAC 2012: A look inside Accellera’s UCIS
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
Cadence joins the dots for verification
The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.
Analog designers ‘need to use digital tools’
Designers working on mixed-signal circuits will benefit from using digital tools, Cadence's SVP of R&D for custom design said at CDNLive EMEA today. But for those who don't a faster fast Spice is on its way.
PLATINUM SPONSORS
View All Sponsors