October 30, 2012
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
October 25, 2012
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
October 25, 2012
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
October 16, 2012
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 8, 2012
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
September 26, 2012
Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.
June 6, 2012
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
June 1, 2012
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
May 16, 2012
The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.
May 15, 2012
Designers working on mixed-signal circuits will benefit from using digital tools, Cadence's SVP of R&D for custom design said at CDNLive EMEA today. But for those who don't a faster fast Spice is on its way.