Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.
The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.
The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
Siemens introduces mPower to bridge the analog-to-digital gap in IR-drop and EM analysis, reflecting the scaling trends in today's ICs.
A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
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