RTL

More than 20 new features and improvements are added to the static functional tool.

Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.