Open-source hardware is going to change the way people buy computing capacity for data centers, says LSI's Rob Ober
The scope of the Low-Latency Interface (LLI) developed by the MIPI Alliance is expanding as it heads towards version 2 – increasing the ways in which a single DRAM array can be shared between SoCs in a mobile phone.
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
Verification drives system-level adoption as sales leap 76%. Virtual prototyping is also on the rise but there are gaps in the tool-set.
At last year’s DAC, leading EDA analyst Gary Smith said chip design had run into a big problem: it was already too expensive to be worthwhile for most companies. Soon afterwards, three companies rang to tell him that the figures were too pessimistic: it was not costing in the region of $75m but perhaps just […]
Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata
Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.
ARM’s annual west coast technical conference opens next Tuesday (October 25) and they’ve made some useful tweaks to how the three-day program will be presented. The first day is dedicated to chip design, while Wednesday and Thursday concentrate on software and systems, as well as modules and boards. For me, with ARM, the focus always […]