Open-Silicon claims RISC-V ultra-low-power first
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
Digital/analog implementation
DAC 2016 preview: Mentor Graphics
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
User2User preview: Silicon Valley edition rolls out this month
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
IP implementation variety drives latest partnerships
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
Samsung taps Mentor tools for higher yielding close-loop DFM
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Tanner EDA @ Mentor Graphics: Steady as she goes
Stability is the watchword as AMS and MEMS specialist Tanner retains much of its independence - a 'start-up with a billion-dollar company behind us'.
TSMC adds Cadence and Imagination subsystems for IoT
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
Broadcom sees Chinese automotive as key to Internet of Things
Comms giant to seek out more local partnerships with China poised to account for a third of car sales with each new vehicle featuring 1,000 semis.
Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
From Darwin to Mao: how multi-patterning could move up the flow
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
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