March 19, 2013
The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.
March 19, 2013
STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.
February 25, 2013
As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.
February 20, 2013
The paper on the 32nm upgrade to Big Blue's family of server chips also detailed how the company is tackling BTI.
February 19, 2013
Keynoter Lisa Su spun a whimsical idea to serious intent as AMD looks to promote its model for heterogeneous architectures
December 13, 2012
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
December 11, 2012
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
December 11, 2012
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
December 4, 2012
Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.
December 4, 2012
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?