Conferences

MEMS relay-based devices offer the ultimate in subthreshold leakage: they don't have any. Design and technology advances are promising to overcome problems with reliability, design and speed, according to Tsu-Jae King Liu of UC Berkeley.

You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.

Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.

Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors

Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.

Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?

Can process migration tools help the yield-challenged and speed the path to 20nm?

What are the chances that FD SOI will become a mainstream process for future nodes?

At last year’s DAC, leading EDA analyst Gary Smith said chip design had run into a big problem: it was already too expensive to be worthwhile for most companies. Soon afterwards, three companies rang to tell him that the figures were too pessimistic: it was not costing in the region of $75m but perhaps just […]

All our news and coverage from DAC 2012 is brought together here. Updates throughout the show.