DVCon: UPF and CPF harmony in low power is only a foundation

By Paul Dempsey |  No Comments  |  Posted: February 25, 2013
Topics/Categories: Blog Topics, Commentary, Conferences, Blog - EDA, - Standards  |  Tags: , , , ,  | Organizations:

On February 4, 2013, the ballot closed on the latest proposed revision to the IEEE 1801 standard for specifying low power intent, better known as the Unified Power Format (UPF). Although the result is likely to be known more widely as something like UPF 2.1, the version on the table is substantially different from the existing 2009 release. For starters, it will have sizeable input from Cadence Design Systems, originator of the rival Si2 standard, the Common Power Format (CPF).

As the new look 1801 moves – hopefully – toward being adopted as a full standard by the IEEE in March, we spoke to Qi Wang, the technical marketing group director at Cadence who has been directly involved in the standard’s development. He reckons to have spent about 250 hours in meetings and many other hours in 1801-related work since the beginning of 2011. Wang acknowledges that it’s been a serious effort all round, including the commitment of his colleagues at users and at rival vendors .

“For three weeks in September 2012, we had at least two eight hour meetings every week” he says. “No kidding – every week.”

Yet the result will still be if not just a beginning then, in his view, only a foundation for low power design. In many ways, it couldn’t be much more.

Methodology convergence

“Our view is that what’s needed between CPF and UPF is methodology convergence first,” Wang says. “Because the technologies you use on top of those are always changing and will always change. They are what make the difference.

“You probably have heard about companies like Cyclos [Semiconductor] doing resonant-clocked design and SuVolta getting 3D numbers out of planar. Low power is a big issue and companies will always be doing something new to differentiate. They all have to.

“It’s the same for the vendors. Rather than the format, it’s about what else you can do.”

In this regard, Wang sees one of the many important illustrations of how 1801 will work in future as its inclusion of a full RTL to place-and-route example demonstrating how to use the revamped standard to drive low power design.

“But it will only demonstrate the most common techniques,” he says. “That’s the purpose because you can never cover every perspective. But this is something the industry can do: not to demand that all customers converge but get as close as possible to allowing them to concentrate on different design technologies and techniques. Convergence helps to reduce the cost of that. It’s about getting the balance between the cost effectiveness and the technology differentiation.”

UPF and CPF continue

So there will still be a CPF and a UPF when the new standard comes out. “But to get to just two is good,” says Wang. “The debate has been a lot about, say, different EDA vendors. But there have also been all the proprietary low power methodologies within users themselves – and a lot of them. So first, you try to reduce to two and then you are going toward one methodology.”

The work on 1801 has also been more user-driven than the wide CPF vs UPF perception might suggest, says Wang.

“In fact, if you look at the companies involved on the committee, there are AMD, ARM, Broadcom, CSR, LSI, Marvell, Mediatek, PMC-Sierra, Qualcomm, Intel, ST, TI, etc. Almost all the big names are there.  As an indicator of the interest level in the methodology convergence, the current 1801 ballot pool is the largest in the history of IEEE-SA for entity-based standards.

“And if you look at one common theme across those customers, they are both CPF and UPF users. Some adopted CPF some time ago. But the bigger thing is that this is all very user-driven. They want multi-vendor flows. They want convergence. And they want to focus on what differentiates their products.”

Beyond the dogma and politics (and the latter will never go away entirely), it is today more important to Cadence that it can consistently point to ongoing co-operation with key partners. For example, it recently unveiled a project jointly undertaken with ARM that links Cadence’s Encounter RTL-to-Signoff flow with the core vendor’s POP core-hardening acceleration IP to optimize power, performance and area for low power. It is also driving hard in the mixed-signal space.

“You have the methodology, but a more interesting question is, ‘Where do you go beyond that?'” says Wang. “Because low power is one area that will not stand still.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors