October 16, 2013

CDNLive calls out for papers

Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.
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October 11, 2013

Verification Futures rolls out in Europe next month

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
October 9, 2013

Jasper preps User Group and Architectural events

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
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October 1, 2013

TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM

TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
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September 12, 2013

SNUG heads to Austin next week

Synopsys user meet in Austin carries forward themes from Boston event.
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September 5, 2013

SNUG Boston focuses on challenges of gigascale IC design

Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
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May 14, 2013

DAC 2013 REMINDER: ‘No Free Monday’

But you can still get in for free by registering for the 'I Love DAC' scheme by this Friday (May 17th).
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May 7, 2013

DAC 2013 Preview V: Rounding out the keynotes

Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.
May 5, 2013

Synopsys users gather for European SNUG meetings

Synopsys users will be gathering at a series of SNUG meetings across Europe over the next month to share insights and experience of using Synopsys tools
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May 5, 2013

IEDM2013 call for papers closing soon

It's time to act if you want your semiconductor device or process research to be considered for presentation at IEDM 2013 in Washington DC this December.
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