Conferences

October 25, 2012

Ambipolar FETs are an each-way bet

Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
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October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 15, 2012

FinFETs face planar fightback at IEDM

Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
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October 9, 2012

Event alert: TSMC Open Innovation Platform

With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
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October 5, 2012

IEF: Process kits for processes that don’t yet exist

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.
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October 4, 2012

IEF: “Industry will have to cooperate”

The semiconductor industry is reaching a crunch point at which companies that form it have to work together much more closely, says Malcolm Penn of Future Horizons.
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October 4, 2012

IEF: Open source hardware to muscle into data centers

Open-source hardware is going to change the way people buy computing capacity for data centers, says LSI's Rob Ober
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October 4, 2012

IEF: Achronix plans embedded FPGA push

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
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October 4, 2012

IEF: Samsung wants a skunk-works

Samsung Electronics is setting up a center in Silicon Valley to try to develop technologies that the company hopes will ultimately drive volume for its chipmaking operation.
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June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
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