IPSoC: Tabula aims for 22nm white-label parts

By Chris Edwards |  1 Comment  |  Posted: December 4, 2012
Topics/Categories: Conferences, Blog - EDA  |  Tags: , , , ,  | Organizations: ,

Tabula is close to taping out its first 22nm-based field-programmable gate array (FPGA), senior director of marketing Marc Miller told delegates at the IPSoC conference today in Grenoble, France.

Miller said Tabula expects to have devices available “early next year”. The company’s parts will be based on finFETs as Tabula, like competitor Achronix, is using Intel’s process to make them. As part of the plan to ramp up sales for the upcoming family of devices, following on from its original 40nm parts, Tabula aims to attract developers of system IP by offering them a sales model analogous to that of the Apple App Store.

During his speech at IPSoC, Miller pointed out that, since its peak in 2000, the number of fabless startups launched each year has continually declined, falling to just two in 2012. Yet the number of acquisitions by larger players, hoping like Broadcom and IDT to achieve technological dominance in sectors such as ethernet and PCI Express controllers, have remained more or less constant. “The result of that is target scarcity,” Miller claimed.

Miller argued there are significant opportunities in high-end networking and data-centre systems as users such as Google and Facebook move from buying predominantly off-the-shelf hardware to specifying their own. If ARM, and potentially other processor IP suppliers, gain a foothold in the server, it could lead to much more use of customised design, some of which will use custom silicon. The problem is that the cost of ASSP design is too high to allow for a healthy pipeline of startups.

One answer is to supply specialised devices such as search accelerators and packet inspectors as FPGAs. This is far from being a new idea. FPGA makers have been happy, in varying degrees, to produce ‘black-top’ devices that sport a customer’s rather than their own logo. Altera has promoted its HardCopy metal-programmed gate array architecture as another lower cost route to custom silicon.

Tabula is trying to go one step further by offering 50/50 revenue split for specialist design companies that want to design ICs instead of a more traditional engagement in which the customer buy parts and, if it wants, pay for them to be custom marked.

One issue for Tabula is that designing for the architecture, which timeslices the logic at high speed, can involve changes to RTL. Miller argued that the density and performance it can offer can make sense to developers of server- or network-oriented designs.

The company started working in this way in 2011, signing a deal with Algo-Logic, a specialist in packet search and PCI Express routing engines.

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