EDA

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.

June's Symposia on VLSI Technology & Circuits will bring together a number of industry trends that extend from implantable biomedical applications to machine learning and cloud computing under the banner of technologies for ‘smart living’.

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.

The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.

The formal verification specialist will be discussing its own experiences and has partnered with users for presentations at DVCon US.

Breker's work towards the portable stimulus roll-out will lead much of its offering later this month in San Jose.

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.