Bulk transistor design aims for near-threshold power cuts

By Chris Edwards |  No Comments  |  Posted: February 21, 2018
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations:

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.

The flat-field transistor is aimed at circuits that operate in the subthreshold and near-threshold regimes built on conventional bulk-CMOS wafers.

The lower variability should make it easier to construct circuits that operate reliably close to the threshold voltage without demanding complex correction strategies or be limited by guardbanding to slower clock rates. As a bulk transistor, it can be implemented on the 40nm to 20nm processes that are now being deployed for IoT-type applications.

According to Semiwise, a 20nm version of the transistor has lower variability than a 14nm finFET or 28nm FDSOI transistor. The local variability is estimated to be around 0.6mV/µ.

Asenov said: “The concept of variability-resistant transistors has been around for a few years however despite significant VC investments many companies have failed to commercialise the technology due to lack of firm understanding of statistical variability and adequate simulations capabilities.”

To address the problem, Asenov’s team developed the transistor structure using the GSS suite for variability-aware TCAD analysis, which Synopsys bought in 2016.

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