7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
EDA
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Anne Cirkel recognized for advancing role of women in electronics design
Mentor executive, former Design Automation Conference chair and Tech Design Forum journal founder to receive Marie R. Pistilli Award at DAC 2018.
SEMI-ESDA tie-up aims to extend EDA’s global reach
Cooperation in key verticals such as automotive and changes for DAC as well as global conference outreach underpin EDA association's move.
Cadence tunes Virtuoso for 5nm and SIP
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
DAC keynotes and sessions aim for AI
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Mentor aims to grow emulation with lower gate-count hardware
Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.