DVCon US 2018 preview: OneSpin Solutions
Formal verification specialist OneSpin Solutions will demonstrate a number of its technologies during DVCon US in San Jose later this month (Feb 26-Mar 1). These will include 360 EC-FPGA, Quantify Fault Observation Coverage and SystemC/C++ Formal Verification Environment, as well as. Other demonstrations will showcase OneSpin’s safety-critical formal verification solutions for automotive and mission-critical applications. The company will be based at Booth #902.
The demos follow on from OneSpin’s recent successful completion of a series of factory inspections and audits of its organization and tool development by the internationally recognized testing body TÜV SÜD. This conformance level enables OneSpin to provide certified formal verification solutions meeting the tool qualification requirements set by functional safety standards (ISO 26262, IEC 61508 and EN 50128/SIL 3). OneSpin’s formal tools and solutions can reach the highest safety integrity levels (ASIL D and SIL 3).
Technical sessions at DVCon US
OneSpin will participate in two sessions in the DVCon technical program.
Sasa Stamenkovic, OneSpin’s senior field application engineer, and Ravi Ram, verification architect and principal engineer at Xilinx, will present “Formal Verification of Floating-Point Hardware with Assertion-Based Verification Intellectual Property (VIP)” during the “Formal and Assertion-Based Verification” session (Wednesday, February 28, 3:00pm-4:30pm, Oak).
OneSpin is also sponsoring a workshop session, “Using Mutation Coverage For Advanced Bug Hunting”, (Thursday, March 1, 2:00pm-3:30pm, Sierra). The speakers will be Nicolae Tusinschi, the company’s product specialist, design verification, and Vladislav Palfy, its global manager for application engineering. The tutorial will take a case-study approach, focusing on complex bug hunting. Attendees will be guided through techniques applicable to various design applications.
