Pillar transistor points to smaller SRAMs at 5nm
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
EDA
Arm Cortex-A processor team focuses on formal
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
IEDM 2018 aims to span quantum, neuromorphic and CMOS devices
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Motion harvester wins MEMS design contest
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
Cadence opens three fronts on mixed-signal failures
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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