June 3, 2013
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 28, 2013
Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
May 22, 2013
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
May 22, 2013
Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
May 21, 2013
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
May 20, 2013
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
May 20, 2013
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
May 14, 2013
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
May 14, 2013
The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.