EDA

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.