EDA

June 3, 2013

UPF group moves to consider system-power issues

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Article  |  Topics: Design to Silicon, Blog - IP  |  Tags: , , ,   |  Organizations:
May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , , , , , ,
May 22, 2013

Mentor adds rapid RFQ to Capital suite

Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
Article  |  Topics: Blog - PCB  |  Tags:   |  Organizations:
May 21, 2013

Aldec automates safety-critical traceability

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
May 20, 2013

Cadence tackles timing signoff with Tempus

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 20, 2013

TVS expands VIP library

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 14, 2013

Jasper adds low-power App to formal family

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
May 14, 2013

Forte Cynthesizer aims at performance, power and ease of use

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.
Article  |  Topics: Blog - EDA, - ESL/SystemC  |  Tags: , , ,   |  Organizations:

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