Timing signoff: maybe it’s time to get rid of the clock

By Chris Edwards |  No Comments  |  Posted: June 4, 2013
Topics/Categories: Blog - EDA  |  Tags: , , , , , , ,  | Organizations: , , ,

The effort needed to deal with process variation in timing signoff could lead to a shift in design, favoring limited use of asynchronous design to avoid the need to perform flat full-chip analysis. It may prove a more viable approach to statistical timing analysis which remains, for the most part, a research topic.

Over the past decade, increasing on-chip variation (OCV) in processes has led to a massive expansion in the number of timing views that need to be generated to predict timing under different process and thermal conditions.

Dipesh Patel, general manager of physical IP at ARM, said at a DAC 2013 panel discussion organized by Cadence Design Systems: “The traditional OCV approach doesn’t help you get to a design database that closes timing.”

Variation sources

There has been a gradual rise in the number of sources of measurable variation, even though technologies such as finFET do remove some such as dopant concentration fluctuation.

“The process nodes are not slowing down and there are a lot of new technology effects that are going to exacerbate variation. From a foundry perspective that is the biggest careabout. Even at 14nm, we are seeing new sources of variation and we will see more at 10nm,” said Richard Trihy, director of global methods at GlobalFoundries. “Double patterning and finFETs bring changes to the way we do design. When we go to triple patterning we may even start to see resistance variation in the nets.

“With finFETs, potentially we are going to see the Miller effect on steroids. It will be interesting to see whether models can give us accurate results on finFETs because of the Miller effect.”

Patel added: “With finFETs, signoff times are going up exponentially because the models are very complicated. But the time we have available to do the design is not changing.”

Asynchronous option

Patel said the clock tree presents one of the biggest problems for timing signoff. “A lot of solutions that we have seen address it at the critical-path level. For clock-tree analysis [designers] are looking at simulating just one corner which is not enough.”

One way around the problem is to remove the global clock tree. “We are looking at how we can solve the problem more at a local level. That was you can solve the problem for a block and, when you integrate the them into an SoC, you don’t have to solve it again,” said Patel.

Instead of forcing all blocks to conform to a global clock, the blocks can communicate asynchronously, a technique known as globally asynchronous, locally synchronous (GALS).

“We are beginning to design blocks of IP that fit into a GALS approach. Because you have smaller codes, you can achieve convergence more quickly. When the block is integrated into an SoC it communicates asynchronously – you’ve decoupled the problem.”

If the architecture does not change, timing signoff under OCV will need to change, although the recent launch of a massively parallel analysis and repair tool by Cadence can bring down runtimes with existing methodologies.

Statistical problems

“There has been a lot of innovation in timing signoff but there hasn’t been enough,” said Tom Spyrou of the office of the CTO at Altera.

Trihy said: “A number of approaches for dealing with variation have been proposed, such as POCV [parametric OCV] and statistical timing. But the barrier to adoption quite frankly is high. Look at SSTA [statistical static timing analysis]. Generating the libraries was painful. The amount of time that it takes to evaluate is immense. The industry is a little burnt-out on these solutions.

Anirudh Devgan, corporate vice president for silicon signoff and verification in Cadence’s silicon realization group, said: “Academia got too defocused on technologies like SSTA that weren’t focused on the mainstream designer.”

Patel added: “SSTA wasn’t good from a methodological perspective. I don’t see us going back to SSTA. The methodology challenges were too great.

“POCV holds some promise but it has some context dependence. We need something that’s context independent. I don’t think as an ecosystem we are coming together to deal with that. The question is: if POCV is the right answer, what’s the best top-down way to get there?”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors