FinFET shift could drive analog automation as layout effects bite

By Chris Edwards |  No Comments  |  Posted: June 7, 2013
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations: , , ,

For analog designers, the arrival of the finFET is turning into something of a technological curate’s egg: good in parts. But it brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.

Scott Herrin, analog design engineer at Freescale Semiconductor, said in a Design Automation Conference (DAC) panel on using finFETs for analog circuits: “There are definitely things that I see and get excited by and there are also things that I get concerned about. The obvious benefits are increased gain and reduced leakage. You do get the issue of quantised width. But from my perspective that’s one of the areas that we were too loose with to begin with. We would probably be better off it we paid closer attention to what matching restrictions we have.”

Better analog properties

Richard Trihy, director of design methodology and design enablement at GlobalFoundries, said: “The reality is we have no choice. To get beyond 20nm we need a new transistor. But there are definitely some advantages in using finFETs. The higher gain and fewer short-channel effects are big wins for digital and analog designers.”

Navraj Nandra, senior director of product marketing for analog IP at Synopsys, cited gain or transconductance as well as improved output conductance and lower noise as improvements in finFET-based processes. “If you look closely, Gm is lower but intrinsic gain, the parameter that matters in design, is better. What is interesting about finFET devices is that you have a better subthreshold characteristic. You can design some really interesting circuits. And the parameters are very well controlled.

“One example is a D/A converter. Because the device matching is better, you can make it smaller. It’s an interesting example of a mixed-signal block getting smaller than 20nm because of the better matching,” said Nandra.

Eric Soenen, academician director at TSMC, said: “Can you do analog? The answer is definitely yes. But the technology is a little more complex. Tools are going to have to be smarter. Parasitics will be harder to extract. We will have to draw a little more CPU time. But the good news is CPU time is not that big a deal.

Parasitic extraction issues

Parasitics and their effects on the design and layout of finFET-based analog circuits are likely to be more difficult to handle than with previous technologies. One reason is the need to account for the vertical as well as horizontal aspects of the trigate structure although Soenen argued that an increase in significant parasitics would also be seen in equivalent FD-SOI processes.

The main effect of the parasitics will be an increase in ‘surprises’, the panelists agreed – in that the performance of the physical circuit could be quite different to that expected from simulation of the schematic version.

“You have to add a lot of parasitics,” said Soenen. “When you back-annotate and put the parasitics in, you will get some surprises there. The models for extraction will be good but it will be computationally complex.”

Trihy said: “There is a question of where the modeling stops and the extraction starts.” He added that effects such as physical stress will change the device properties and are currently difficult to predict but noted: “We are likely to see fewer layout-dependent effects overall so that may simplify the job of going from the schematic through layout and back.”

Restrictions drive automation

Analog designers will have to deal with a significantly reduced voltage range compared with most CMOS processes. Digital circuits are likely to take advantage of a lower supply voltage to cut active power – going down to just 0.5V.

Soenen said: “We plan on having 1.8V available. But 5V becomes a bit more challenging.”

The result of the lower voltage for mixed-signal design is likely to be much greater use of digital-assist techniques, Soenen said. “With finFETs you can build very good switches. Anything that is switched-capacitor works well and you will have very dense, fast logic. People have been talking about these techniques for a long time. People will now be taking advantage of them.”

Width quantisation, caused by the requirement to use a discrete number of fins, potentially could lead to greater use of layout-synthesis techniques.

“With 14nm, because of the quantization, layout synthesis becomes much more practical,” said Trihy. “There are potential solutions that tools vendors could put forward that get around the stress and layout challenges. The inherent gridding and snapping that’s required to lay out devices makes the layout easier for tools. Sometimes these changes put other solutions in reach.”

“We’ve used some automation to convert a width into the equivalent number of fins. If the simulation gives you an ideal width that doesn’t fit the grid, the tool will calculate a quantized version,” said Nandra.

Soenen said: “Design synthesis has not taken off yet. Maybe traditionally design was too easy. But if it gets too difficult to predict layout effects manually and tools can automate that process, that could be very powerful.”

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors