EDA

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.

Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.

Express Logic has launched a graphical user interface (GUI) software stack for resource-light 32bit microcontrollers running the company's ThreadX RTOS.

Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.

Valor additions aim to deliver shopfloor data to PCB ERP systems in real time... for the first time. And could boost ROI beyond 70%.

Digia has launched a graphical user interface development suite based on Qt that is aimed at embedded devices running Linux and Android.

Mentor's new version of its RTOS targets once high-cost flexibility with secure and reliable in-operation upgrades and app swap-outs for medical, industrial and smart energy.

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.

Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more

Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.