EDA

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).

Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.

Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.

Synopsys users will be gathering at a series of SNUG meetings across Europe over the next month to share insights and experience of using Synopsys tools

CDNLive EMEA opens 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in real projects.

Dr Chenming Hu joins Mentor CEO Wally Rhines and Xilinx SVP Victor Peng to keynote free day-long User2User in San Jose on April 25th, capping a full technical program.

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.

At DATE 2013, Synopsys senior vice president Antun Domic, described how techniques for the latest nodes are being rolled back into mature nodes, all the way to 180nm.

In the first of our weekly DAC 2013 previews, we discuss program highlights with general chair Yervant Zorian, including an expanded Designer Track, keynotes and golden jubilee celebrations.

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.