Real Intent updates X verification tool
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
EDA
SNUG heads to Austin next week
Synopsys user meet in Austin carries forward themes from Boston event.
Speed boost for Palladium emulators
Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
SNUG Boston focuses on challenges of gigascale IC design
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
ARM buys securable display controller
ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.
IP providers make plans for the internet of things
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
CDNLive Boston to tackle mixed-signal design, host exhibit
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
Three Accellera proposals aim for better TLM
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.