“The flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off,” says Sarath Kirihennedge, senior manager of product engineering.
“Other legacy solutions in the market try to offer a high-capacity gate solution, but sacrifice coverage and analysis accuracy to get it. Meridian’s hierarchical flow avoids the compromises found with abstract modeling and the use of waivers.”
There is plenty of fighting talk in the CDC space right now as the inherent challenges continue to climb up the design agenda for ever more complex systems-on-chip. At this month’s Design Automation Conference, ARM technologists talked about the coming-of-age of GALS (globally asynchronous, locally synchronous) strategies that are likely to heat things up further.
The Meridian suite also looks to build on work to create a full RTL sign-off flow, particularly with regard to the IP, reuse and power-driven aspects of CDC. In May, Real Intent announced a pact to integrate its CDC technologies with DeFacTo’s design-for-test tools.
With the launch of Meridian 5.0, Real Intent has integrated the suite with Synopsys’ market-leading Verdi Automated Debug System and introduced several other new features. These include:
- A correct-by-configuration design setup to improve analysis and reporting, and thereby ease sign-off.
- More support for CDC constraints, including set clock groups and naming schemes.
- An updated and faster formal analysis engine.
- Extended SystemVerilog support for interface elements and, specifically, the language’s synthesizable subset.
The new generation suite has also added enhancements for bus handling. Reset analysis now addresses glitches in both asynchronous and synchronous domains. And there is analysis for crossings that may be blocked by environment definition.
Meridian 5.0 is available from July. Pricing depends on the product configuration.