September 5, 2013
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
June 18, 2013
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
May 14, 2013
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.