May 20, 2013
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
May 20, 2013
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
May 14, 2013
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
May 14, 2013
The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.
May 14, 2013
Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.
May 8, 2013
ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.
May 7, 2013
Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).
May 7, 2013
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
May 7, 2013
Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.