EDA

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference

Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.

ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.