power intent


May 27, 2015

Mentor zooms in on power peaks with emulator interface

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
May 18, 2015

Sonics readies fine-grained power-gating architecture

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
June 5, 2013

Jasper, Duolog bring formal verification to IP specification and assembly, low-power design

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: ,   |  Organizations: ,
May 29, 2012

DAC 2012: Atrenta to automate production of power-intent constraints

Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.
Article  |  Topics: Commentary, Conferences  |  Tags: , , , , ,   |  Organizations:

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