August 12, 2013
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
July 30, 2013
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
July 15, 2013
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
July 8, 2013
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
June 18, 2013
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
June 14, 2013
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
June 7, 2013
The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 5, 2013
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
June 4, 2013
The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.