June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
June 14, 2013
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
June 7, 2013
The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 5, 2013
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
June 4, 2013
The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.
June 3, 2013
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 28, 2013
Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
May 22, 2013
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
May 22, 2013
Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
May 21, 2013
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.