Master the verification challenge of PCIe-based NVMe storage
NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
EDA
Wally Rhines looks beyond ‘endless verification’ to the system era
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
Cadence tunes fixed-point DSP for neural networks
Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
ARM deploys data-center tech to study verification patterns
ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
DVCon China looms as submission deadline for Europe approaches
The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
Cadence cuts up DRC for speed
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Leverage AI and centralized processing for L-5 autonomous vehicles
L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.
Bridging the gap between IP development and qualification for P&R
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
Combining 1D and 3D CFD simulation for piping systems
Computational fluid dynamics now addresses more of the simulation activities required for complex systems in a single methodology.
The return of the CEO Outlook
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.