EDA

Mentor, a Siemens business, has released details on its varied activities at DAC 2017, ranging from panels to technical papers.

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.

The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.

Austemper Design Systems has launched a portfolio of tools that span the development lifecycle of projects that need to demonstrate functional safety.

DAC's traditional training day is expanding into the field of machine learning this year in Austin.

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.