EDA sets sail in a ‘sea of processors’

By Chris Edwards |  1 Comment  |  Posted: March 12, 2013
Topics/Categories: Blog - EDA  |  Tags: , , , , , ,  | Organizations: , ,

There are two ways you can look at the purchase of Tensilica by Cadence Design Systems. One is as a move to mirror Synopsys, which acquired the ARC family of configurable processors as part of the much wider Virage Logic deal, in terms of intellectual property (IP) cores. The other is as part of a larger shift in the way that chip designs are done.

Tensilica co-founder and CTO Chris Rowen published his book “Engineering the Complex SoC” five years ago. But some of the ideas behind that took shape much earlier – not that long after the formation of the company in 1997 – at a point when the concept of configurable IP, let alone configurable processors, was comparatively new.

Although it is always possible to paint these processors as “competitors to ARM” – and it probably helped raise funding if VCs thought it was the case – they have largely been the hidden, deeply embedded workhorses sitting inside SoCs. The outside world regarded the designs as hardware but chugging away inside was a processor running software with some modified instructions to improve speed or reduce power consumption on tasks such as MP3 decoding.

But the long-term plan was to move from a design in which processors were used tactically, to augment fixed hardware and to provide some flexibility, to the concept of a “sea of processors” – a grid of software-programmed cores.

I first heard Rowen use the term during a panel at the 2000 DAC in downtown Los Angeles on the future of SoC design.

“SoC will become a sea of processors,” said Rowen. “You will have ten to maybe a thousand processors on a chip. The individual processors on a chip are tiny, so you can do that. You end up with something that is almost the best of both worlds, between the flexibility of FPGAs and processors and hard-wired logic.”

Presaging the current issue with energy consumption, Professor Bob Broderson from the University of California at Berkeley, said there would be an issue with pure software processing. “Software architectures are at least 100 times less efficient in power and area than hardware. That gap will increase.”

Broderson’s plan was to implement strips of massively parallel processing capacity and not attempt to time-multiplex processor logic – essentially the main cause of the power consumption. Professor Mark Horowitz of Stanford University returned to this issue close to ten years later, proposing a compromise between hardware and software.

Horowitz and colleagues used the Tensilica tools to see how such a design approach might turn out, describing it at venues such as the 2010 DATE. Horowitz explained that it might be a way to solve chip design’s pressing problem of cost. “The ASIC business is dying because the design cost is upward of $20m,” he said. “Writing Verilog is the wrong thing to do: we want to write something that has a longer lifetime than just a single design.”

He said he had been to an electronic hobbyists’ show: “At first I was offended when they had a microcontroller behind every blinky light. But then I thought: ‘why not?’”

In the run up to the 2010 talks, Horowitz said his team experimented with the idea of a “chip generator” based on heterogeneous multiprocessors.

“We use the standard software trick of adding a layer of indirection. You can tune the resources you care about and even change the hardware support. Then you generate the optimised chip,” Horowitz explained, adding that the first implementation is a multiprocessor generator. “We are using Tensilica because it makes it easier to do.

“Using this generic multiprocessor, we looked at what happens if we do H.264 video encoding. Initially, it was 400 to 600 times slower than real time. The students worked to speed up the implementation by using generic data-parallel optimisations. That led to about an order of magnitude improvement. But to really get improvements we had to do very customised changes to the implementation for the particular application we were running. We got to within a factor of three what the ASIC got.”

WIth the existing licensing deals that Tensilica has, Cadence can augment its IP offering. But, potentially, the combination of design tools, in an era where software design is becoming more critical, and the configurable processor concept could bring the sea-of-processors architecture, and the advantages it may bring, just that little bit closer.

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