Samsung lines up tool providers for finFET tapeouts

By Chris Edwards |  1 Comment  |  Posted: December 21, 2012
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations: , , ,

The finFETs are coming. Having gone to tapeout on IBM’s upcoming 14nm finFET process, ARM and Cadence Design Systems have now taped out a design on Samsung’s. At the same time, Synopsys said that it has taped out a test-chip design on the 14nm process as well.

The IBM project involved a Cortex-M0 processor. The latest ARM and Cadence design uses the more complex Cortex-A7 – the little part of the first Big-Little pairing with the A15. The device was designed using a complete Cadence RTL-to-signoff flow, including Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System, and Encounter Power System.

In addition to the ARM Cortex-A7 processor, the test chip includes ARM Artisan standard-cell libraries, next-generation memories and general purpose I/Os.

Cadence’s Bluefin project

In a note sent to online newsletter Deepchip, Cadence’s John Murphy reported that the design took eight weeks to complete and claimed that the test chip is the first to put control of the double-patterning layers in the hands of the designers:

“Before Project Bluefin, double patterned designs were handed-off to the foundry as if there was only one mask for the double patterned metal layers. (The foundry would then perform layer assignment as part of the decomposition process for mask prep. This lack of colorization adds uncertainty to the timing model, which the fabs guardband against.)

“On the Bluefin project, we did the layer assignment inside our Encounter Digital, which we then handed off to the foundry and preserved through mask prep…Then, because Cadence RC extraction has been rewritten to recognize colors, the timing model uncertainty is reduced – thus no need for fab guardbanding!”

Synopsys test chip

Synopsys said its test chip is intended to validate Samsung’s 14nm FinFET process as well as Synopsys’ DesignWare Embedded Memories with embedded self-test and repair. The test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs. The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate process performance.

Mentor design-rule and test support

Mentor Graphics said it is providing post-tapeout support. Dr Kyu-Myung Choi, senior vice-president of the system LSI infrastructure design center at Samsung’s device solutions unit said: “The design rules for 14nm are extremely complex with the introduction of FinFETs in addition to double patterning (DP) layers. It is critical that physical design, verification and testing tools are intimately aligned with the manufacturing processes of the target foundry. Since Samsung also uses the Mentor Calibre solution for its own IC development, designers using it will get accurate and immediate feedback so they can co-optimize the design process.”

Calibre creates decomposed double patterning (DP) layouts that are compliant with of Samsung’s 14nm lithography. It also provides designers feedback on design rules for FinFETs.

Mentor and Samsung are also performing production test diagnosis by exchanging information between Mentor’s Tessent tools and the Calibre Pattern Matching facility to quickly identify and eliminate design-specific yield limiting features during design ramp up.

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