June 3, 2013
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 20, 2013
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
May 14, 2013
Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.
May 8, 2013
ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.
May 7, 2013
Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).
May 7, 2013
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
May 7, 2013
Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.
April 29, 2013
CDNLive EMEA opens 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in real projects.
March 19, 2013
Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.
March 13, 2013
Experts from Cadence and Synopsys talk about the implications for designers of the rise of ‘systems of systems’.