verification

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.

Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.

DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.

As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.