Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
Verification conference DVCon is expanding into Europe with a two-day conference and show at the Hilton in Munich, Germany.
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
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