June 10, 2014
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
March 28, 2014
Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
February 21, 2014
Verification conference DVCon is expanding into Europe with a two-day conference and show at the Hilton in Munich, Germany.
January 14, 2014
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
November 20, 2013
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
October 9, 2013
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
September 10, 2013
Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
September 5, 2013
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
May 22, 2013
DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.
May 20, 2013
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.