The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
Aldec updates tools to add support for the latest release of the VHDL verification methodology.
Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.
At DAC this week, Verifyter is offering a limited number of companies free six-month licences of its regression-analysis tool Pindown.
The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.
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