verification

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.

DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation

The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.

Aldec updates tools to add support for the latest release of the VHDL verification methodology.

Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.

As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.