verification

September 2, 2015

Early registration opens for DVCon Europe 2015

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
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July 8, 2014

Focusing coverage for system-level integration

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
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July 3, 2014

DVCon India heads to Bangalore

As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
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June 25, 2014

Accellera releases version 1.2 of UVM

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
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June 10, 2014

Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
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March 28, 2014

Software quality acquisition to bring Synopsys “new friends”

Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
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February 21, 2014

DVCon sets up in Europe

Verification conference DVCon is expanding into Europe with a two-day conference and show at the Hilton in Munich, Germany.
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January 14, 2014

Cadence updates Incisive with formal, CRV, wreal additions

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
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November 20, 2013

Complexity to force shift to four-stage verification

The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
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October 9, 2013

Jasper preps User Group and Architectural events

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
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