verification

April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
April 4, 2013

Accellera extends verification work to legacy environments

Accellera Systems Initiative has created a working group to look at one of the knottiest problems in IC design: to simplify the job of checking designs when the bits come from so many sources and use languages that were not built for interoperability.
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November 19, 2012

‘Process and metrics before tools for better verification’

Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
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October 8, 2012

Synopsys buys EVE and the death of dogma

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
May 29, 2012

DAC 2012: Accellera takes first step to a real coverage standard

UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.
Article  |  Topics: Blog Topics, Conferences, Blog - EDA, - Standards, Verification  |  Tags: , , ,   |  Organizations:
April 25, 2012

Mentor unveils second-generation Veloce emulator

Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , ,   |  Organizations:
March 16, 2012

DATE notebook: Aldec builds in more support for VHDL methodology

Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
February 27, 2012

Synopsys verification IP launch has bite

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

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