Agnisys has developed a sequence generator that and format for creating and checking register-control sequences. Semifore has launched a tool and supporting language to specify status register behavior and address maps.
Agnisys’ ISequenceSpec lets designers describe sequences for register-based initialization, configuration, and testing that are then used by the tool to generate both UVM models and firmware code to allow the sequences to be tested.
“Users can enter the sequence of an operation in the form of a common specification and ISequenceSpec will convert that into a portable sequence library for a variety of domains,” said Anupam Bakshi.
Sequences can use register information written using industry standard formats such as IP-XACT, SystemRDL and RALF, or custom formats that may take the form of CSV, XML, Word, or Excel files. ISequenceSpec will generate sequences that can be imported into the Cadence Design Systems’ Perspec verification environment and Mentor Graphics’ Questa inFact testbench-automation tool.
Three parts to CoStar
CoStar Design Director from Semifore is built around three components: a compiler, language, and configuration tool. The platform supports Semifore’s own specification formats and industry standards, adding a collection of functions that are not currently available in UVM, IP-XACT, or SystemRDL.
The CSRSpec language provides a single source to specify the register behavior and address map hierarchy of a chip. When compiled, the language expands to human readable RTL suitable for synthesis.
The CSRCompiler tool contains a cross-compiler engine with more than a thousand functional, behavioral, syntactic, and semantic error checks. Semifore said it will more than one million configuration and status registers in minutes and contains a linter to check the incoming register specifications.
The CSRConfigurator customizes the output of CSRCompiler without scripting, providing design-team members with outputs suitable for their specific design flows.