verification

September 22, 2017

5G and automotive provide applications focus for DVCon Europe

The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
August 11, 2017

Keynotes announced for DVCon Europe

DVCon Europe 2017 has announced two keynote speakers for the conference to be held in Munich, Germany in mid-October.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
June 15, 2017

Early access view of portable-stimulus standard released

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
June 15, 2017

DAC 2017 preview: Breker

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
April 28, 2017

ARM deploys data-center tech to study verification patterns

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
March 8, 2017

Verification Futures tackles safety and security

The Verification Futures conference organized by European EDA consultancy TV&S returns for its seventh year in early April with a focus on safety and security in the growing area of cyber-physical systems.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: , ,
October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , ,   |  Organizations:
October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:

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