verification

December 18, 2015

Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
November 16, 2015

Cadence shifts emulation to the data center

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
October 8, 2015

Expanding role of UVM takes center stage at DVCon Europe

Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
September 25, 2015

DVCon Europe initial technical program unveiled

DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
September 2, 2015

Early registration opens for DVCon Europe 2015

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
July 8, 2014

Focusing coverage for system-level integration

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 3, 2014

DVCon India heads to Bangalore

As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
June 25, 2014

Accellera releases version 1.2 of UVM

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
June 10, 2014

Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
March 28, 2014

Software quality acquisition to bring Synopsys “new friends”

Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
Article  |  Topics: Verification  |  Tags: ,   |  Organizations:

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