June 10, 2014
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
May 24, 2014
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
April 10, 2014
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
November 19, 2013
Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.
May 20, 2013
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
April 29, 2013
DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.
November 19, 2012
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
March 16, 2012
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
February 27, 2012
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.