Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.
University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
DVCon Europe brings design and verification insights to Munich next week.
DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.
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