Test and Verification Solutions (TVS) has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
The TVS verification IP provides access to the source code and tests that are mapped to the protocol specification so that the user can see the intention of the test. The asureVIP library components contain traffic generators that allows the chip integrator to generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.
Protocols handled by the verification IP components include the MIPI RFFE and DSI interfaces, the I2C and SPI serial buses, Ethernet networking and PCIExpress and USB 3.0 high-speed I/O channels.
Mike Bartley, CEO of TVS, said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon.”
TVS wrote the UVM-compliant verification IP components in native System Verilog. TVS said it is able to provide customized VIP “under flexible ownership arrangements”. The TVS agile development process also means that the verification IP is delivered in a number of short ‘sprints’ to allow an early start on verification.